Zelinda's design approach begins with the study of a range of possible designs, both conventional and new innovative approaches. These designs are reviewed at the most fundamental level and each independently optimised for the particular situation. The design options are then traded off against one another and the most promising selected to form the baseline design. The key system parameters of the baseline design, such as frequency plan, digital word size, sampling rate etc. are then subject to a detailed analysis to generate a fully specified design ready for simulation.
Preliminary analysis and simulation of design alternatives are typically performed at an early stage to select and refine the design concept. If necessary a "bit true" simulation can then be constructed. To this end Zelinda have a library of custom bit true C++ models of typical communications building blocks. These can be used to build a simulation model of a proposed design that can be validated under the anticipated operating conditions.
The Zelinda design team has developed design techniques that use progressively more digital processing and correspondingly less analogue and RF circuitry. In particular by using sub-sampling and over-sampling techniques it is possible to sample the received signal at a high IF frequency, or in some cases the RF signal may be sampled directly. Carrier recovery loops are now often closed entirely within the sampled time domain leaving the RF part of the receiver responsible simply for amplification, filtering and downconversion by a fixed frequency. Zelinda are thus able to specify the RF design requirements relatively simply. It is then often possible to build a demonstration model of the transponder using commercial, connectorised, RF components. For the production version of the transponder the RF detailed design is usually subcontracted.
With the increasing use of ASIC and FPGA technology an ever-larger proportion of digital electronic design at Zelinda is performed using hardware description languages such as VHDL. The design process requires as a minimum writing an RTL (Register Transfer Level) description of the design together with a "test bench" that provides simulation stimulus and checks the design functionality. Higher level abstractions of the design may also be used in more complicated designs. The VHDL is written in a hierarchical structure so that individual modules can be independently tested and this also permits easy module reuse in later projects. On completion of VHDL validation the design is synthesized into the target FPGA (or ASIC) and the pinouts frozen. The top-level schematic can then be completed, a PCB laid out and the prototype manufactured.
In parallel with the increasing use of hardware digital signal processing within communications equipment there has been a corresponding increase in the use of software for the overall control and lower speed signal processing. Zelinda designers have been involved in projects using a variety of processors: both dedicated DSP chips (such as the Motorola 56000 range); as well as more general-purpose processors such as Mil Spec 1750. To provide the highest possible execution speed these processors are traditionally programmed in assembler language.
For ground based systems the availability of high speed PCs is now making it possible to use low cost hardware and high level languages to perform functions that would traditionally have required development of custom-designed hardware. Software solutions are expected to provide significant savings in cost and development time in future designs.
Prototype Construction & Test
Prototypes are constructed and tested in house. The Zelinda Lab is equipped with a suite of standard test equipment including oscilloscopes, spectrum analyzers, noise and interference test sets and BER testers.
Zelinda's expertise is primarily in design so having tested the prototype subsequent manufacturing is either subcontracted or an engineering data package is handed over to the client who then assumes responsibility for manufacture.